1. Field of the Invention
The present invention relates to an integrated circuit, and more particularly to an internal signal replication device and method.
2. Description of the Related Art
To precisely generate clock signals, integrated circuits include duty cycle compensation circuits to compensate for duty cycle variances of an externally provided clock signal. A typical integrated circuit with a duty cycle compensation circuit will now be described with reference to FIG. 1. FIG. 1 is a block diagram of an integrated circuit 100 with a duty cycle compensation circuit 110. The duty cycle compensation circuit 110 includes a DLL 111 to generate N delayed versions of an externally generated clock signal ECLK and a phase mixer 112 to generate a replica clock signal CLK_R according to the N delayed clock signals. A data output unit 120 receives cell data from a memory cell array (not shown) and transmits the cell data DQ responsive to the replica clock signal CLK_R. Integrated circuit 100 may be a memory as disclosed in Korean patent laid-open publication No. 2003-88232.
The relationship among the external clock signal ECLK, the replica clock signal CLK_R, and the memory cell data DQ is illustrated in FIG. 2. FIG. 2 is a timing diagram illustrating the operation of integrated circuit 100 shown in FIG. 1. Referring to FIG. 2, the integrated circuit 100 receives external clock signal ECLK and generates the replica clock signal CLK_R from the external clock signal ECLK. Since the integrated circuit 100 compensates for the duty cycle of the external clock signal ECLK when generating the replica clock signal CLK_R, there is a delay or latency between the reception of the external clock signal ECLK and the generation of the replica clock signal CLK_R. The integrated circuit 100 transmits the cell data DQ responsive to the replica clock signal CLK_R.
Testing the internal signals of integrated circuit 100, e.g., the delayed clock signals generated by the DLL 111 or signals for controlling the operation of memory cell array (not shown), remains difficult. For instance, to measure the internal signals the package containing the integrated circuit 100 must be decapped and probed using a probe tip or measured using electron beam (E-beam) probing with an oscilloscope. This testing process is not only inconvenient and complicated, but the results are potentially inaccurate since the internal signals are measured in a substantially different environment. In other words, decapping the package containing the integrated circuit 100 exposes the circuit to external noise, and thus internal signals are likely to be inaccurately measured.